The present invention relates generally to AFG (analog floating gate) circuits, and more particularly to circuits that compensate for loss of charge stored on analog floating gates used in extremely low power integrated circuits, such as voltage reference circuits.
Floating gate field effect transistors have long been used as digital memory elements. More recently, floating gate field effect transistors have been used in extremely low power analog integrated circuits, such as precision voltage reference circuits.
FIG. 1 shows a conventional EEPROM (electrically erasable programmable read only memory) cell 1 which includes a N-channel floating gate MOS (metal oxide semiconductor) field effect transistor or “sense transistor” or “read transistor” 3 having a floating gate electrode 2 disposed on a thin oxide layer over the channel region of the transistor. EEPROM memory is designed to retain a sufficient level of charge on the floating gate MOS transistor over the desired lifetime of the memory that an undesired change of a stored state due to lost charge never occurs. Some charge may be lost from the floating gate of the EEPROM cell 1, but never enough to switch the stored state. Floating gate 2 typically is composed of suitably doped polycrystalline silicon, and the thin oxide layer typically is roughly 70 Angstroms to 120 Angstroms thick. A portion of floating gate 2 functions as one plate of a “control gate” capacitor 5, the other plate of which is connected to a control gate terminal 7 on which a control gate voltage VCG may be applied.
A portion of floating gate 2 also is connected to one plate of a thin oxide capacitor 4 which is referred to as a “tunneling region”. The other plate of tunneling region 4 is connected to a terminal 6 on which a programming voltage VTG may be applied to permanently or semi-permanently write a “1” or a “0” voltage level onto floating gate 2.
Control gate capacitor 5 has a larger capacitance than tunneling region 4 and sense transistor 3. The larger capacitance of control gate capacitor 5 allows the voltage on floating gate 2 to be controlled by means of control gate terminal 7. The amount of voltage control one has over the floating gate 2 depends on the voltage coupling to floating gate 2 from control gate terminal 7. The coupling is equal to the capacitance of control gate 5 divided by the total capacitance of floating gate 2. Control gate capacitor 5 has a large capacitive voltage coupling from terminal 7 to floating gate 2. Therefore, the amount of charge tunneling through control gate capacitor 5 is small. That is, the voltage VCG on terminal 7 minus the voltage on floating gate 2 is small, e.g., less than 10% of VCG−VTG. Stated differently, the voltage on floating gate 2 follows the control gate voltage VCG.
The amount of tunneling through tunneling region 4 depends on the amount of voltage drop across its tunneling oxide, with a higher voltage drop across tunneling region 4 causing a larger amount of tunneling current through it and vice versa. Tunnel gate capacitor 4 has a relatively small capacitive voltage coupling between terminal 6 and floating gate 2, so the amount of charge tunneling through tunnel gate capacitor 4 is relatively large compared to the amount of charge tunneling through control gate capacitor 5. That is, the voltage VTG on terminal 6 minus the voltage on floating gate 2 is relatively large, e.g., typically approximately 90% of VCG−VTG.
FIG. 1 also shows an optional P-channel (or N-channel) floating gate MOS transistor 9 having its floating (i.e., electrically isolated) gate connected to and continuous with floating gate 2 of sense transistor 3 for the purpose of providing faster hot electron injection programming of a “0” or “low” voltage level onto floating gate 2 than may be achieved by use of tunneling region 4. It is possible to use P-channel (or N-channel) floating gate transistor 9 to accomplish HCI (hot carrier injection) programming. Both options inject electrons onto floating gate 2, causing negative voltage bias thereon. However, using a P-channel transistor as floating gate transistor 9 allows use of a lower programming voltage.
FIG. 2 shows a “conceptual” equivalent circuit that may be helpful in understanding tunneling region 4 in FIG. 1. Tunneling region 4 may be conceptualized as a capacitor 4A coupled in parallel with back-to-back zener diodes 4B and 4C, as shown. A circuit symbol for tunneling region 4 is shown to the right of the conceptual equivalent circuit. A current tunnels from a first plate of capacitor 4A through a thin oxide (i.e., a “tunnel oxide”) to a second plate of capacitor 4A if sufficient voltage is applied across the tunneling oxide of capacitor 4A to cause charge to flow through its tunneling oxide to the first plate of capacitor 4A. The tunneling current may be thought of as electrons (e−) flowing from the first plate to the second plate of capacitor 4A if the zener voltage of one of zener diodes 4B or 4C is exceeded. The charge resulting from the tunneling current then remains trapped on the second plate of capacitor 4A as long as the applied voltage between the two terminals of the tunneling region is kept below the threshold voltage of the tunnel oxide.
Referring again to FIG. 1, the programming accuracy of, and charge “loss” from, floating gate 2 of sense transistor 3 in EEPROM cell 1 are not a significant problem as long as the stored potential on floating gate 2 is sufficient to keep read transistor 3 in a preset “1” state or a preset “0” state. The term “charge loss” as used herein may refer to either an undesired increase or an undesired decrease in the amount of charge trapped/stored on the floating gate. In EEPROM memory a negative (electrons) or positive (holes) charge may be stored on the floating gate, so a net negative or a net positive charge may be lost. That may erroneously switch the stored logic state from a “1” to a “0” or visa versa, depending on the reference voltage used for detection of the stored logic level.
Sense transistor 3 in Prior Art FIG. 1 also may be used in an analog circuit. However, in AFG (analog floating gate) circuit applications, both the programming accuracy of the amount of charge stored on a floating gate and the amount of undesired charge “loss” from the electrically floating gate in an analog circuit application may be problematic because the resulting voltage of the floating gate directly and continuously affects the achievable accuracy of the application circuit in which the floating gate transistor 3 is used. This is in contrast to EEPROM circuits, in which a small increase or decrease in the amount of trapped charge has no effect on the stored “1” or “0” state except in the narrow transition region between an “on” condition and an “off” condition of the read transistor.
Charge stored on a floating gate creates a voltage difference between the floating gate (i.e., the floating plate of a tunneling region or a control gate capacitor) and a reference plate of the tunneling region or control gate capacitor. The floating gate voltage is determined mainly by a reference voltage applied to the control gate terminal 7 and by old that the charge stored on the floating gate 2. The voltages applied to the other terminal (of sense transistor 3 and tunnel region terminal 6) have a smaller impact due to their smaller capacitance. The equation for floating gate voltage is given by:Vfg=Kcg*Vcg+Ktg*Vtg+Ks*Vss+Kd*Vsd+Kb*Vbs+Q/Ctotal,where each of the “K” values refers to the coupling coefficient for a corresponding terminal associated with the floating gate and is given by the capacitance of that terminal divided by the total capacitance Ctotal of the floating gate, and where:
Vfg is the floating gate voltage,
Kcg is the control gate capacitance divided by total capacitance,
Vcg is the control gate voltage,
Ktg is the tunnel gate capacitance divided by total capacitance,
Vtg is the tunnel gate voltage,
Ks is the floating gate overlap of source capacitance,
Vss is the source voltage,
Kd is the floating gate overlap of drain capacitance,
Vsd is the drain voltage,
Kb is the floating gate overlap of transistor channel (bulk) capacitance,
Vbs is the bulk voltage,
Q is the charge on the floating gate, and
Ctotal is equal to the sum of the control gate capacitance, the tunnel gate capacitance, the source overlap capacitance, the drain overlap capacitance, and the bulk overlap capacitance.
If some or all of the charge trapped on the floating gate 2 is lost (i.e., unintentionally modified/degraded), the effective threshold voltage of sense transistor 3 changes. This, of course, may cause an unacceptable loss in the accuracy of analog circuitry in which floating gate transistor 3 is used.
The mechanisms that may cause loss of charge from a floating gate include FNT (Fowler-Nordheim Tunneling), SILC (stress induced leakage current), mobile ion contamination, and/or HCI (Hot Carrier Injection). Providing additional charge onto the floating gate is usually accomplished by FNT tunneling. FNT tunneling may be used for the AFG (analog floating gate) applications described herein and also for other known voltage reference circuits. HCI is common in OTP (one time programmable) memory, and flash memory. FNT tunneling may be considered to be a high voltage process. For a 70 Angstrom tunneling oxide, roughly 12 volts applied for a duration of approximately 100 milliseconds may be used to program the floating gate. Electrons may be tunneled onto the floating gate by applying roughly 12 volts to the control gate and grounding the tunnel gate, or alternatively, electrons may be tunneled away from the floating gate by applying roughly 12 volts to the tunnel gate and grounding the control gate, depending on whether the resulting charge on the floating gate needs to be increased or decreased. Thus, FNT tunneling may be used to accomplish both programming and erasing of the floating gate voltage.
The other common way of programming a floating gate is by using hot carrier injection. This is accomplished by injecting high-energy electrons through the gate oxide of a sensing transistor, rather than by using a FNT charge tunneling mechanism. A typical voltage used to accomplish hot carrier injection is approximately 5 to 6 volts on the drain of a P-channel MOS programming transistor, such as transistor 9 in FIG. 1, to cause injection of hot electrons onto the floating gate. (More specifically, the bulk and drain electrodes of the programming transistor are connected together and the source electrode is grounded.) This has the effect of increasing the effective threshold voltage of a N-channel sense transistor (e.g., transistor 3 in FIG. 1) so that a greater positive gate-to-source voltage is required to turn it on. As long as the drain voltage of the sense transistor does not exceed approximately 5 to 6 volts, essentially no change in its floating gate charge will occur.
FNT tunneling may be used to provide any charge on the floating gate, typically to provide an amount of charge that results in a floating gate voltage in the range of roughly −5 volts to +5 volts. In contrast, hot electron injection may only be used to program or increase the threshold voltage of an N-channel sense transistor from an initial low level up to approximately 5 volts. (Hot electron injection makes the floating gate more negative with respect to ground, and therefore a higher control gate voltage then is required to turn on an N-channel sense transistor.) A common approach to programming of a floating gate is to program one polarity of the floating gate voltage by using hot electron injection and to program the other polarity using FNT tunneling. Several known AFG precision manufacturing process require 2 or 3 levels of polycrystalline silicon (hereinafter referred to as “poly”) and associated additional masking steps to create unique tunneling structures. Consequently, use of the bipolar FNT tunneling technique as used in such structures is not very scalable to present state-of-the-art wafer fabrication processes.
The floating gate of an AFG device is capacitive in nature and therefore may be influenced by external capacitive coupling not only by means of a control gate capacitor, but also by other external capacitive coupling. A control gate voltage may be applied to one plate of the control gate capacitor, the other plate of which is part of the floating gate. Any charge introduced by any means onto and stored on the floating gate causes an offset to a voltage applied to the other plate of the control gate capacitor.
AFG technology has been used primarily in low power analog integrated circuit applications, including voltage reference circuits. In “nanopower” applications wherein the quiescent current needs to be less than a micrompere, the problem of providing accurate reference voltages is very important and challenging because the resistors of the voltage reference circuits must be very large, and consequently the associated thermal noise becomes unacceptably large. Conventional bandgap voltage reference circuits for generating accurate reference voltages usually consume substantial amounts of current, because reducing resistor noise in a bandgap voltage reference circuit typically requires increasing the amount of current therein (since the input-referred thermal noise is inversely proportional to the square root of current in the bandgap voltage reference circuit). For some applications, use of a AFG voltage reference circuit has been found to be a good practical solution to this problem.
FIG. 3 shows a basic prior art AFG-based precision voltage reference circuit 10-1. Voltage reference circuit 10-1 includes an error amplifier 11 having its (+) input coupled to a floating gate 12, part of which is shared with a first plate of a tunneling region 13. The (+) input of amplifier 11 is connected to the gate of a (+) input transistor (not shown) of amplifier 11. Another part of floating gate 12 forms a first plate of another tunneling region 14, and also forms a first plate of a reference or storage capacitor 15. The second plate of tunneling region 13 may be coupled to a positive programming voltage VTRp1, and a second plate of tunneling region 14 may be coupled to a negative programming voltage VTRn1. The second plate of reference capacitor 15 is connected to ground. The output 16 of voltage reference circuit 10-1 is the output reference voltage Vout=VREF, and is connected to a first plate of a feedback capacitor 20, the second plate of which is connected to another floating gate conductor 17.
Part of floating gate 17 forms the gate of a (−) input transistor (not shown) of error amplifier 11. Another part of floating gate 17 forms a first plate of a tunneling region 18, and yet another part of floating gate 17 forms a first plate of another tunneling region 19. The second plate of tunneling region 18 may be coupled to a positive programming voltage VTRp2, and the second plate of tunneling region 19 may be coupled to a negative programming voltage VTRn2. In the prior art, both positive and negative tunneling regions conduct simultaneously under control of a feedback loop. This simultaneous conduction approach to programming of floating gate voltages results in accuracy sufficient for precision analog use, but requires some additional process complexity for the tunneling structure.
AFG-based voltage reference circuit 10-1 of FIG. 3 may be used to replace a conventional bandgap voltage reference circuit. Those skilled in the art know that a bandgap reference voltage is established by the difference between a pair of bipolar transistor collector currents. Most of the noise generated in a conventional bandgap voltage reference circuit is caused by the two collector currents, and it is necessary to increase those collector currents in order to reduce the noise of the bandgap voltage reference circuit. In contrast, the tunneled charge for AFG-based voltage reference circuit 10-1 is stored on a floating gate rather having a reference voltage maintained by flow of current through a resistance, so there are no bipolar transistor collector currents and therefore no shot noise. Furthermore, a bandgap voltage inherently is a fixed voltage determined by the bandgap of the semiconductor material and its temperature, whereas an AFG-based reference voltage is not fixed but is readily adjustable or programmable to any desired value.
FIG. 4 shows another conventional AFG-based voltage error or reference circuit 10-2 in which the output 16 of reference amplifier 11 generates an output reference voltage Vout=VREF and is connected to a first plate of feedback capacitor 20. The second plate of feedback capacitor 20 is formed by a portion of floating gate 12. Another part of floating gate 12 forms the (−) input transistor 22 of reference amplifier 11. C11 is the capacitance of the portion of floating gate 12 that forms the gate of input transistor 22. Floating gate 12 also forms a first plate of a tunneling region 24, a second plate of which is connected to ground. The capacitance of tunneling region 24 is C13. The voltage Vfg1 of floating gate 12 may be set to approximately Vout/2. The (+) input transistor 23 of reference amplifier 11 is a floating gate transistor, the gate of which is formed by a portion of floating gate 17. Floating gate 17 also forms a first plate of a tunneling region 25 and a first plate of a control gate capacitor (or reference capacitor or storage capacitor) 26. The second plate of tunneling region 25 and the second plate of control gate capacitor 26 are connected to ground. C21 is the capacitance of the gate portion of (+) input transistor 23. The capacitance of tunneling region 25 is C23, and the capacitance of control gate capacitor 26 is C22. The voltage Vfg2 of floating gate 17 also may be set to Vout/2. Input transistors 22 and 23 typically are MOS floating gate transistors connected in a differential configuration.
In FIG. 4, all of the gate oxides, tunnel region oxides and capacitor dielectric oxides may be “thin oxides”, with thicknesses in the range about 70 to 120 Angstroms. The e− symbols and associated arrows indicate electrons tunneling through the various floating gate tunneling oxides in the directions indicated. In many of the likely circuit applications, analog floating gates are provided for both of the differential input transistors of the amplifier. The arrow and e− symbol next to storage capacitor 26 indicates that tunneling could occur in it because of the thin oxide.
The e− symbols indicate the direction of electron flow during normal operation and/or during shelf life. The minute amount of charge loss during powering up and down of the circuit is insignificant. The current flowing through the various capacitances in FIG. 4 depends on the electric fields across their associated oxides. When AFG-based voltage reference circuit 10-2 device is OFF (i.e., not powered up), the charge on the floating gates tends to leak off over time due to the electric fields caused by the charge stored on each floating gate. During operation, the electric fields across the various capacitances are different due to the different applied voltage biases. Under the influence of a bias voltage, electrons may flow onto a floating gate, instead of flowing from the floating gate. The electron flow will be in the direction toward the side of a capacitance which is biased at the higher voltage.
It is believed that the closest prior art is directed mainly to the initial programming of the analog floating gates and to long-term retention of the programmed charge on the floating gates. It also is believed that the prior art does not disclose passive or active direct compensation for loss of charge the analog floating gates which generally occurs over the product lifetime. When “indirect” compensation for loss of trapped charge on floating gates has been attempted, it is believed to have taken the form of either additional re-programming or re-calibration of analog floating gate circuits.
Thus, there is an unmet need for a circuit and method for compensating loss of trapped charge on a floating gate in an AFG (analog floating gate) circuit.
There also is an unmet need for a inexpensive circuit and method that makes it more practical for precision analog floating gate circuits to retain their accuracy over acceptable circuit lifetimes.
There also is an unmet need for a way to avoid the need to provide complex circuitry to compensate for undesired loss of charge on analog floating gates of AFG circuitry.
There also is an unmet need for a way to avoid calibration cycles or reprogramming cycles to compensate for undesired loss of charge on analog floating gates of AFG circuitry.